Differential clocks are used in many high-speed mixed-signal applications. A differential clock is typically formed from two component (e.g., single-ended) clock signals. Ideally, the two component signals are complementary in nature (e.g., the first component signal is in a logic-high state whenever the second component signal is in a logic-low state, and vice-versa) and have a 50% duty cycle (e.g., each component signal is in the logic-high state for 50% of a given clock period and in the logic-low state for 50% of the clock period). Complementary clock signals are desirable to avoid short-circuit currents in differential circuits, while a 50% duty cycle is desirable to achieve accurate sampling in double-data rate (DDR) systems. Because high-speed applications often have very precise timing requirements, the differential clocks may be generated using crystal oscillators and/or voltage-controlled oscillators (VCOs).